As the design rule of metal oxide semiconductor field effect transistor (MOSFET) devices that have recently been developed reduces to sub-100 nm or less, a channel length accordingly is also decreased. As a result, in implementing a threshold voltage (Vt) target of a MOSFET device required in a specific device, an existing planar transistor structure is limited in terms of process and device. Thus, in order to prevent the short channel effect of the MOSFET device, active research has been done on a MOSFET device having a three-dimensional recessed gate in which the gate is formed in a groove formed by etching a silicon substrate.
However, the conventional three-dimensional recessed gate structure is problematic in that there is no increased on-current effect relative to an increased channel area, considering the channel area is increased.